In hard disk drives (HDDs), the read channel typically includes two Phase-Locked Loop (PLL) circuits that generate two synthesized clocks, where the frequency of one clock is programmed to match the user data frequency, while the frequency of the second clock is programmed to match the servo pattern frequency. Because the clocks are generated with analog phase locked loop (PLL) circuits, the phase relationship between the two clocks is an unknown and random value when the clocks are powered on, or when the frequency of either clock is changed. In certain applications, such as self-servo write, and so forth, the ability to determine the relationship between the clocks would provide system benefits.